The present invention generally relates to semiconductor process integration, and more specifically relates to a semiconductor device which has Sixe2x80x94Ge on Silicon and a layer of Sixe2x80x94Ge forms the base of a bipolar transistor and a layer of Silicon on the layer of Sixe2x80x94Ge forms the emitter of the bipolar transistor, and a method of making a semiconductor device where the method includes depositing Sixe2x80x94Ge on Silicon, and the method provides that a layer of Sixe2x80x94Ge forms the base of a bipolar transistor and a layer of Silicon on the layer of Sixe2x80x94Ge forms the emitter of the bipolar transistor.
The semiconductor industry has been constantly striving to improve the data transfer speed for communications using silicon-based semiconductor devices (i.e., semiconductor products). To date, various schemes and improvements have been proposed, both in the area of process technology and circuit design, in order to handle the higher frequencies required for data transmission with lower power consumption.
Present semiconductor devices are typically configured such that FET transistors and other devices, such as speed-performance sensitive parts of a circuit, are disposed on Silicon. As such, carrier flow is not forced to a surface channel region. This causes short channel effects, thereby resulting in leakage and/or increased power consumption. Additionally, as transistor sizes shrink, the electron hole carrier mobility and the device noise needs to be improved to provide adequate performance and circuit design margin.
A general object of an embodiment of the present invention is to provide a semiconductor device which has at least a region that provides Sixe2x80x94Ge on Silicon and a Silicon layer on the Sixe2x80x94Ge, where the semiconductor device is configured such that the Sixe2x80x94Ge forms the base of a bipolar transistor and the Silicon on the Sixe2x80x94Ge forms the emitter of the bipolar transistor.
Another object of an embodiment of the present invention is to provide a method of making a semiconductor device, where the method includes depositing Sixe2x80x94Ge on Silicon, and the method provides that a layer of Sixe2x80x94Ge forms the base of a bipolar transistor and a layer of Silicon on the layer of Sixe2x80x94Ge forms the emitter of the bipolar transistor.
Still another object of an embodiment of the present invention is to provide a method of making semiconductor device which eliminates processing steps which are typically required to form an emitter over the base region.
Still yet another object of an embodiment of the present invention is to provide a semiconductor device which includes a strained silicon layer which provides increased mobility of electrons through the base.
Yet still another object of an embodiment of the present invention is to provide a semiconductor device which has a thin base region with a high dopant concentration and abrupt doping profiles.
Another object of an embodiment of the present invention is to provide a semiconductor device which provides retardation in dopant diffusion out for the base region, caused by the incorporation of dopants near the junction interfaces.
Another object of an embodiment of the present invention is to provide a method of making a semiconductor device wherein oxygen is incorporated into the base at the emitter to base junction to increase barrier potential and subsequent emitter efficiency of the device.
Another object of an embodiment of the present invention is to provide a method of making a semiconductor device which consumes less dynamic power due to a higher operating frequency.
Another object of an embodiment of the present invention is to provide a method of making a semiconductor device which provides that base contact is made by either tungsten plugs or by the use of poly silicon.
Briefly, and in accordance with at least one of the forgoing objects, an embodiment of the present invention provides a semiconductor device which has at least a region where Sixe2x80x94Ge is disposed on Silicon. Specifically, the semiconductor device preferably includes Sixe2x80x94Ge disposed on a Silicon substrate. The semiconductor device may include a Silicon region which does not include any Sixe2x80x94Ge, but preferably also includes an Sixe2x80x94Ge region which includes Sixe2x80x94Ge on Silicon. Preferably, the Sixe2x80x94Ge is provided as an Sixe2x80x94Ge layer which is disposed between a Silicon layer and the Silicon substrate, and the Sixe2x80x94Ge forms the base of a bipolar transistor and the Silicon layer on the Sixe2x80x94Ge forms the emitter of the bipolar transistor.
A method of making such a semiconductor device is also provided, and includes steps of forming an oxide layer on a Silicon substrate, masking at least a portion of the oxide layer to define a deep collector implant and N well implants, Vt adjusting the implant to define the CMOS (FET) devices, mask at least a portion of the oxide layer and implant dopant to form a collector region of a bipolar transistor, masking to define one or more selective areas within a chip on which epitaxial Sixe2x80x94Ge and a Silicon layer will be grown, removing (such as by wet etching) at least a portion of the oxide layer in order to expose a portion of the Silicon substrate and create an undercut in open areas defined by the previous masking step, epitaxially growing an Sixe2x80x94Ge layer on the exposed portion of the Silicon substrate, epitaxially growing a Silicon layer on the Sixe2x80x94Ge layer, if regions are not doped then masking and implanting dopant to define the base and emitter regions of the bipolar transistor, and continuing manufacture of the device by forming one or more bipolar and CMOS devices and continuing until the end of the line to define interconnect and passivation.